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PM25LD512/010/ 020 confidential information chingis technology corp. 1 draft date: august, 2010, rev:0.4 features ? single power supply operation - low voltage range: 2.3 v C 3.6 v ? memory organization - PM25LD512: 64k x 8 (512 kbit) - pm25ld010: 128k x 8 (1 mbit) - pm25ld020: 256k x 8 (2 mbit) ? cost effective sector/block architecture - 512kb : uniform 4kbyte sectors / two uniform 32kbyte blocks - 1mb : uniform 4kbyte sectors / four uniform 32kbyte blocks - 2mb : uniform 4kbyte sectors / four uniform 64kbyte blocks ? low standby current 1ua (typ) ? serial peripheral interface (spi) compatible - supports single- or dual-output - supports spi modes 0 and 3 - maximum 33 mhz clock rate for normal read - maximum 100 mhz clock rate for fast read ? page program (up to 256 bytes) operation - typical 2 ms per page program ? sector, block or chip erase operation - maximum 10 ms sector, block or chip erase ? low power consumption - typical 10 ma active read current - typical 15 ma program/erase current ? hardware write protection - protect and unprotect the device from write operation by write protect (wp#) pin ? software write protection - the block protect (bp2, bp1, bp0) bits allow partial or entire memory to be configured as read- only ? high product endurance - guaranteed 200,000 program/erase cycles per single sector - minimum 20 years data retention ? industrial standard pin-out and package - 8-pin 150mil soic - 8-pin 208mil soic for pm25ld040 - 8-pin 300mil pdip for pm25ld040 - 8-contact wson - 8-pin tssop - lead-free (pb-free), halogen-free package general description the PM25LD512/010/020 are 512kbit/ 1mbit / 2mbit se rial peripheral interface (spi) flash memories, pro viding single- or dual-output. the devices are designed to support a 33 mhz clock rate in normal read mode, a nd 100 mhz in fast read, the fastest in the industry. the devices use a single low voltage power supply, wide operating voltage ranging from 2.3 volt to 3.6 volt, to perfo rm read, erase and program operations. the devices can be programmed in standard eprom programmers. the PM25LD512/010/020 are accessed through a 4-wire spi interface consisting of serial data input/outp ut (slo), serial data output (so), serial clock (sck), and chip enable (ce#) pins. they comply with all recognized command codes and operations. the dual- output fast read operation provides and effective s erial data rate of 200mhz. the devices support page program mode, where 1 to 2 56 bytes data can be programmed into the memory in one program operation. these devices are divided in to uniform 4 kbyte sectors or uniform 32 kbyte blocks.(pm25ld020 is uniform 4 kbyte sectors or uni form 64 kbyte). the PM25LD512/010/020 are manufactured on pflash?s advanced non-volatile technology. the devices are offered in 8-pin soic 150mil, 8-contact wson and 8 -pin tssop. the devices operate at wide temperature s between -40c to +105c. 512kbit/ 1 mbit / 2 mbit single operating voltage serial flash memory with 100 mhz dual-output spi bus interface
PM25LD512/010/ 020 confidential information chingis technology corp. 2 draft date: august, 2010, rev:0.4 product ordering information pm25ldxxx - s c e environmental attribute e = lead-free (pb-free) and halogen- free package temperature range c = commercial grade (-40c to +105c) package type s = 8-pin soic 150mil (8s) b = 8-pin soic 208mil (8b) p = 8-pin pdip 300 mil (8p) k = 8-contact wson (8k) pflash device number PM25LD512/010/020 part number operating frequency (mhz) package temperature range PM25LD512-sce pm25ld010-sce pm25ld020-sce 100 8s 150mil soic PM25LD512-kce pm25ld010-kce pm25ld020-kce 100 8k wson (back side metal) pm25ld040-pce 100 8p 300mil pdip pm25ld040-bce 100 8b 208mil soic PM25LD512-dce pm25ld010-dce pm25ld020-dce 100 8-pin tssop commercial grade (-40 o c to +105 o c)
PM25LD512/010/ 020 confidential information chingis technology corp. 3 draft date: august, 2010, rev:0.4 connection diagrams 5 6 7 8 1 23 4 vcc hold# sck sio so gnd wp# ce# 5 6 7 8 1 23 4 vcc hold# sck sio so gnd wp# ce# pin descriptions symbol type description ce# input chip enable: ce# low activates the devices internal circuitries for device operation. ce# high deselects the devices an d switches into standby mode to reduce the power consumption. when a device is not selected, data will not be accepted via the serial input pin (slo), and the serial output pin (so) will remain in a high impeda nce state. sck input serial data clock sio input/output serial data input/output so output serial data output gnd ground vcc device power supply wp# input write protect: a hardware program/erase p rotection for all or part of a memory array. when the wp# pin is low, memory array write-protection depends on the setting of bp2, bp1 and bp0 bits in the stat us register. when the wp# is high, the devices are not write-protected. hold# input hold: pause serial communication by the master device without resetting the serial sequence. ce# ce# so wp# gnd vcc hold# sck sio sio sck hold# vcc so wp# gnd 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 8 - pin soic 8 - contact wson 8 - pin tssop 8 - pin pdip
PM25LD512/010/ 020 confidential information chingis technology corp. 4 draft date: august, 2010, rev:0.4 block diagram sio
PM25LD512/010/ 020 confidential information chingis technology corp. 5 draft date: august, 2010, rev:0.4 spi modes description multiple PM25LD512/010/020 devices can be connected on the spi serial bus and controlled by a spi master, i.e. microcontroller, as shown in figur e 1. the devices support either of two spi modes: mode 0 (0, 0) mode 3 (1, 1) the difference between these two modes is the clock polarity when the spi master is in stand-by mode: t he serial clock remains at 0 (sck = 0) for mode 0 an d the clock remains at 1 (sck = 1) for mode 3. plea se refer to figure 2. for both modes, the input data i s latched on the rising edge of serial clock (sck), a nd the output data is available from the falling edge of sck. figure 1. connection diagram among spi master and s pi slaves (memory devices) figure 2. spi modes supported msb msb sck sck so sio input mode mode 0 (0, 0) mode 3 (1, 1) spi master (i.e. microcontroller) cs3 cs2 cs1 spi memory device spi memory devic e spi memory device spi interface with (0,0) or (1,1) sd i o sdi sck sck sck sck so so so si o si o s io ce# ce# ce# wp# wp# wp# hold# hold# hold# note: 1. the write protect (wp#) and hold (hold#) signals sh ould be driven high or low as
PM25LD512/010/ 020 confidential information chingis technology corp. 6 draft date: august, 2010, rev:0.4 system configuration the PM25LD512/010/020 devices are designed to inter face directly with the synchronous serial periphera l interface (spi) of the motorola mc68hcxx series of microcontrollers or any spi interface-equipped syst em controllers. the devices have two superset features that can be enabled through specific software inst ructions and the configuration register: block no. block size (kbytes) sector no. sector size (kbytes) address range sector 0 (1) 4 000000h - 000fffh sector 1 4 001000h - 001fffh : : : sector 7 4 007000h - 007fffh sector 8 4 008000h - 008fffh sector 9 4 009000h - 009fffh : : 000000h - 006fffh sector 15 4 00f000h - 00ffffh block 2 32 " " 010000h - 017fffh block 3 32 " " 018000h - 01ffffh memory density 1 mbit 512 kbit 32 32 block 0 block 1 table 1-1. block/sector addresses of PM25LD512/010/ 020 memory density block no. block size (kbytes) sector no. sector size (kbytes) address range sector 0 4 000000h - 000fffh sector 1 4 001000h - 001fffh : : : block 0 64 sector 15 4 00f000h - 00ffffh sector 16 4 010000h - 010fffh sector 17 4 011000h - 011fffh : : : block 1 64 sector 31 4 01f000h - 01ffffh : : : : : 2 mbit block 3 64 : 4 030000h C 03ffffh
PM25LD512/010/ 020 confidential information chingis technology corp. 7 draft date: august, 2010, rev:0.4 registers (continued) status register refer to tables 5 and 6 for status register format and status register bit definitions. the bp0, bp1, bp2, and srwd are volatile memory cells that can be written by a write status registe r (wrsr) instruction. the default value of the bp2, b p1, bp0 were set to 0 and srwd bits was set to 0 at factory. once a 0 or 1is written, it will not b e changed by device power-up or power-down, and can only be altered by the next wrsr instruction. the status register can be read by the read status register (rdsr). refer to table 10 for instruction set. the function of status register bits are described as follows: wip bit : the write in progress (wip) bit is read-only, and can be used to detect the progress or completio n of a program or erase operation. when the wip bit i s 0, the device is ready for a write status registe r, program or erase operation. when the wip bit is 1 , the device is busy. wel bit : the write enable latch (wel) bit indicates the status of the internal write enable latch. when the wel is 0, the write enable latch is disabled, and all write operations, including write status register, page program, sector erase, block and chip erase operati ons are inhibited. when the wel bit is 1, write opera tions are allowed. the wel bit is set by a write enable (wren) instruction. each write register, program an d erase instruction must be preceded by a wren instruction. the wel bit can be reset by a write disable (wrdi) instruction. it will automatically b e the reset after the completion of a write instruction. bp2, bp1, bp0 bits : the block protection (bp2, bp1, bp0) bits are used to define the portion of the mem ory area to be protected. refer to tables 7, 8 and 9 fo r the block write protection bit settings. when a defined combination of bp2, bp1 and bp0 bits are set, the corresponding memory area is protected. any program or erase operation to that area will be inhibited. note: a chip erase (chip_er) instruction is executed successfully only if all the block protection bits are set as 0s. srwd bit : the status register write disable (srwd) bit operates in conjunction with the write protecti on (wp#) signal to provide a hardware protection mode. when the srwd is set to 0, the status register is not write-protected. when the srwd is set to 1 an d the wp# is pulled low (v il ), the volatile bits of status register (srwd, bp2, bp1, bp0) become read-only, and a wrsr instruction will be ignored. if the srwd is set to 1 and wp# is pulled high (v ih ), the status register can be changed by a wrsr instruction. table 5. status register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 srwd1 reserved bp2 bp1 bp0 wel wip default (flash bit) 0 0 0 0 0 0 0
PM25LD512/010/ 020 confidential information chingis technology corp. 8 draft date: august, 2010, rev:0.4 registers (continued) table 6. status register bit definition bit name definition read- /write non-volatile bit bit 0 wip write in progress bit: "0" indicates the device is ready "1" indicates a write cycle is in progress and the device is busy r no bit 1 wel write enable latch: "0" indicates the device is not write enabled "1" indicates the device is write enabled (default) r/w no bit 2 bp0 bit 3 bp1 bit 4 bp2 block protection bit: (see table 7 and table 8 for details) "0" indicates the specific blocks are not write-pro tected (default) "1" indicates the specific blocks are write-protect ed r/w yes bits 5 - 6 n/a reserved: always "0"s n/a bit 7 srwd status register write disable: (see table 9 for det ails) "0" indicates the status register is not write-prot ected (default) "1" indicates the status register is write-protecte d r/w yes table 8. block write protect bits for PM25LD512/010 /020 bp1 bp0 PM25LD512a pm25ld010a pm25ld020 0 0 none none none 0 1 none upper quarter (block 3) 018000h - 01ffffh upper quarter (block 3) 030000h - 03ffffh 1 0 none upper half (block 2 & 3) 010000h - 01ffffh upper half (block 2 & 3) 020000h - 03ffffh 1 1 all blocks 000000h - 00ffffh all blocks 000000h - 01ffffh all blocks 000000h - 03ffffh status register bits protected memory area
PM25LD512/010/ 020 confidential information chingis technology corp. 9 draft date: august, 2010, rev:0.4 registers (continued) protection mode the PM25LD512/010/020 have two types of write- protection mechanisms: hardware and software. these are used to prevent irrelevant operation in a possibly noisy environment and protect the data integrity. hardware write-protection the devices provide two hardware write-protection features: a. when inputting a program, erase or write status register instruction, the number of clock pulse is checked to determine whether it is a multiple of ei ght before the executing. any incomplete instruction command sequence will be ignored. b. the write protection (wp#) pin provides a hardware write protection method for bp2, bp1, bp0 and srwd in the status register. refer to the status register description. c. write inhibit is 1.8v, all write sequence will b e ignored when vcc drop to 1.8v and lower software write protection the PM25LD512/010/020 also provides two software write protection features: a. before the execution of any program, erase or wr ite status register instruction, the write enable latch (wel) bit must be enabled by executing a write enable (wren) instruction. if the wel bit is not enabled first, the program, erase or write register instruction will be ignored. b. the block protection (bp2, bp1, bp0) bits allow part or the whole memory area to be write-protected. table 9. hardware write protection on status register srwd wp# status register 0 low writable 1 low protected 0 high writable 1 high writable
PM25LD512/010/ 020 confidential information chingis technology corp. 10 draft date: august, 2010, rev:0.4 device operation the PM25LD512/010/020 utilize an 8-bit instruction register. refer to table 10 instruction set for det ails of the instructions and instruction codes. all instruc tions, addresses, and data are shifted in with the most significant bit (msb) first on serial data input (si). the input data on si is latched on the rising edge of s erial clock (sck) after chip enable (ce#) is driven low ( v il ). every instruction sequence starts with a one-byte instruction code and is followed by address bytes, data bytes, or both address bytes and data bytes, depending on the type of instruction. ce# must be driven high (v ih ) after the last bit of the instruction sequence has been shifted in. the timing for each instruction is illustrated in t he following operational descriptions. table 10. instruction set instruction name hex code operation command cycle maximum frequency rdid abh read manufacturer and product id 4 bytes 100 mhz jedec id read 9fh read manufacturer and product id by jedec id command 1 byte 100 mhz rdmdid 90h read manufacturer and device id 4 bytes 100 mhz wren 06h write enable 1 byte 100 mhz wrdi 04h write disable 1 byte 100 mhz rdsr 05h read status register 1 byte 100 mhz wrsr 01h write status register 2 bytes 100 mhz read 03h read data bytes from memory at normal read mode 4 bytes 33 mhz fast_read 0bh read data bytes from memory at fast read mode 5 byt es 100 mhz frdo 3bh fast read dual output 5 bytes 100 mhz page_ prog 02h page program data bytes into memory 4 bytes + 256b 50 mhz sector_er d7h/ 20h sector erase 4 bytes 100 mhz block_er d8h block erase 4 bytes 100 mhz chip_er c7h/ 60h chip erase 1 byte 100 mhz hold operation hold# is used in conjunction with ce# to select the PM25LD512/010/020. when the devices are selected and a serial sequence is underway, hold# can be used to pause the serial communication with the master device without resetting the serial sequence. to pause, hold# is brought low while the sck signal is low. to resume serial communication, hold# is brought high while the sck signal is low (sck may still toggle during hold). inputs to slo will be ignored while so is in the high impedance state.
PM25LD512/010/ 020 confidential information chingis technology corp. 11 draft date: august, 2010, rev:0.4 device operation (continued) rdid command (read product identification) operation the read product identification (rdid) instruction is for reading out the old style of 8-bit electronic signature, whose values are shown as table of id definitions. this is not same as rdid or jedec id instruction. its not recommended to use for new design. for new design, please use rdid or jedec id instruction. the rdes instruction code is followed by three dumm y bytes, each bit being latched-in on si during the r ising edge of sck. then the device id is shifted out on s o with the msb first, each bit been shifted out durin g the falling edge of sck. the rdes instruction is ended by ce# goes high. the device id outputs repeatedly if continuously send the additional clock cycles on sc k while ce# is at low. table 11. product identification product identification data first byte 9dh manufacturer id second byte 7fh device id: device id 1 device id 2 PM25LD512 05h 20h pm25ld010 10h 21h pm25ld020 11h 22h figure 3. read product identification sequence 0 1 8 31 38 39 46 47 54 high impedance device id1 device id1 device id1 sck ce# si so instruction 9 7 1010 1011b 3 dummy bytes
PM25LD512/010/ 020 confidential information chingis technology corp. 12 draft date: august, 2010, rev:0.4 device operation (continued) jedec id read command (read product identification by jedec id) operation the jedec id read instruction allows the user to read the manufacturer and product id of devices. re fer to table 11 product identification for pflash manufacturer id and device id. after the jedec id read command is input, the second manufacturer id (7fh) is shifted out on so with the msb first, foll owed by the first manufacturer id (9dh) and the device i d (22h, in the case of the pm25ld020), each bit shift ed out during the falling edge of sck. if ce# stays lo w after the last bit of the device id is shifted out, the manufacturer id and device id will loop until ce# i s pulled high. figure 4. read product identification by jedec id r ead sequence sck ce# si instruction 1001 1111b 0 8 15 23 24 31 7 16 high impedance so device id2 manufacture id1 manufacture id2
PM25LD512/010/ 020 confidential information chingis technology corp. 13 draft date: august, 2010, rev:0.4 device operation (continued) rdmdid command (read device manufacturer and device id) operation the rdmdid instruction allows the user to read the manufacturer and product id of devices. refer to ta ble 11 product identification for pflash manufacturer i d and device id. the rdmdid command is input, followed by a 24-bit address pointing to an id tabl e. the table contains the first manufacturer id (9dh) and the device id (22h, in the case of the pm25ld020), and is shifted out on so with the msb first, each b it shifted out during the falling edge of sck. if ce# stays low after the last bit of the device id is shifted out, the manufacturer id and device id will loop until ce# i s pulled high. figure 5. read product identification by rdmdid rea d sequence
PM25LD512/010/ 020 confidential information chingis technology corp. 14 draft date: august, 2010, rev:0.4 note : (1) address a0 = 0, will output the 1st manufacture id (9dh) first -> device id1 -> 2nd manufacture id (7fh) address a0 = 1, will output the device id1 -> 1st manufacture id (9d) -> 2nd manufacture id (7fh)
PM25LD512/010/ 020 confidential information chingis technology corp. 15 draft date: august, 2010, rev:0.4 device operation (continued) write enable operation the write enable (wren) instruction is used to set the write enable latch (wel) bit. the wel bit of the PM25LD512/010/020 is reset to the write Cprotected state after power-up. the wel bit must be write enabled before any write operation, including secto r, block erase, chip erase, page program and write sta tus register operations. the wel bit will be reset to t he write-protect state automatically upon completion o f a write operation. the wren instruction is required before any above operation is executed. figure 6. write enable sequence wrdi command (write disable) operation the write disable (wrdi) instruction resets the wel bit and disables all write instructions. the wrdi instruction is not required after the execution of a write instruction, since the wel bit is automatically res et. figure 7. write disable sequence si o sio
PM25LD512/010/ 020 confidential information chingis technology corp. 16 draft date: august, 2010, rev:0.4 device operation (continued ) rdsr command (read status register) operation the read status register (rdsr) instruction provide s access to the status register. during the execution of a program, erase or write status register operation , all other instructions will be ignored except the rdsr instruction, which can be used to check the progres s or completion of an operation by reading the wip bit o f status register. figure 8. read status register sequence wrsr command (write status register) operation the write status register (wrsr) instruction allows the user to enable or disable the block protection and status register write protection features by writin g 0s or 1 s into the volatile bp2, bp1, bp0 and srwd bits. figure 9. write status register sequence device operation (continued) sio sio
PM25LD512/010/ 020 confidential information chingis technology corp. 17 draft date: august, 2010, rev:0.4 read command (read data) operation the read data (read) instruction is used to read memory data of a PM25LD512/010/020 under normal mode running up to 33 mhz. the read instruction code is transmitted via the sl o line, followed by three address bytes (a23 - a0) of the first memory location to be read. a total of 24 add ress bits are shifted in, but only a ms (most significant address) - a0 are decoded. the remaining bits (a23 C a ms ) are ignored. the first byte addressed can be at any memory location. upon completion, any data on the sl will be ignored. refer to table 12 for the r elated address key. the first byte data (d7 - d0) addressed is then sh ifted out on the so line, msb first. a single byte of dat a, or up to the whole memory array, can be read out in on e read instruction. the address is automatically incremented after each byte of data is shifted out. the read operation can be terminated at any time by dri ving ce# high (v ih ) after the data comes out. when the highest address of the devices is reached, the addr ess counter will roll over to the 000000h address, allo wing the entire memory to be read in one continuous read instruction. table 12. address key address pm25ld020 pm25ld010 PM25LD512 a n ( a ms C a 0) a17 - a0 a16 - a0 a15 - a0 don't care bits a23 C a18 a23 C a17 a23 C a16 figure 12. read data sequence sio
PM25LD512/010/ 020 confidential information chingis technology corp. 18 draft date: august, 2010, rev:0.4 device operation (continued) fast_read command (fast read data) operation the fast_read instruction is used to read memory data at up to a 100 mhz clock. the fast_read instruction code is followed by three address bytes (a23 - a0) and a dummy byte (8 clocks ), transmitted via the si line, with each bit latched- in during the rising edge of sck. then the first data byte addressed is shifted out on the so line, with each bit shifted out at a maximum frequency f ct , during the falling edge of sck. the first byte addressed can be at any memory location. the address is automatically incremented after each byte of data is shifted out. when the hi ghest address is reached, the address counter will roll o ver to the 000000h address, allowing the entire memory to be read with a single fast_read instruction. the fast_read instruction is terminated by driving ce# high (v ih ). figure 13. fast read data sequence sio sio
PM25LD512/010/ 020 confidential information chingis technology corp. 19 draft date: august, 2010, rev:0.4 device operation (continued ) frdo command (fast read dual output) operation the frdo instruction is used to read memory data on two output pins each at up to a 100 mhz clock. the frdo instruction code is followed by three address bytes (a23 - a0) and a dummy byte (8 clocks ), transmitted via the si line, with each bit latched- in during the rising edge of sck. then the first data byte addressed is shifted out on the so and sio lines, w ith each pair of bits shifted out at a maximum frequenc y f ct , during the falling edge of sck. the first bit (m sb) is output on so, while simultaneously the second bi t is output on sio. the first byte addressed can be at any memory location. the address is automatically incremented after each byte of data is shifted out. when the hi ghest address is reached, the address counter will roll o ver to the 000000h address, allowing the entire memory to be read with a single frdo instruction. frdo instructi on is terminated by driving ce# high (v ih ). figure 14. fast read dual-output sequence 0 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31 ... instruction = 0011 1011b ... 23 22 21 3 2 1 0 3 - byte address ce# sck sio so high impedance 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 ce# sck sio so high impedance data out 1 data out 2
PM25LD512/010/ 020 confidential information chingis technology corp. 20 draft date: august, 2010, rev:0.4 device operation (continued ) page_prog command (page program) operation the page program (page_prog) instruction allows up to 256 bytes data to be programmed into memory i n a single operation. the destination of the memory t o be programmed must be outside the protected memory area set by the block protection (bp2, bp1, bp0) bi ts. a page_prog instruction which attempts to program into a page that is write-protected will be ignored . before the execution of page_prog instruction, the write enable latch (wel) must be enabled through a write enable (wren) instruction. the page_prog instruction code, three address bytes and program data (1 to 256 bytes) are input v ia the slo line. program operation will start immediat ely after the ce# is brought high, otherwise the page_prog instruction will not be executed. the internal control logic automatically handles the programming voltages and timing. during a program operation, all instructions will be ignored except the rdsr instruction. the progress or completion of the program operation can be determined by reading the wip bit in status register via a rdsr instruction. if the wip bit is 1, the program operation is still in progress. if wip bit is 0, the program operation has completed. if more than 256 bytes data are sent to a device, t he address counter rolls over within the same page, th e previously latched data are discarded, and the last 256 bytes data are kept to be programmed into the page. the starting byte can be anywhere within the page. when the end of the page is reached, the address wi ll wrap around to the beginning of the same page. if t he data to be programmed are less than a full page, th e data of all other bytes on the same page will remai n unchanged. note: a program operation can alter 1s into 0s , but an erase operation is required to change 0s back to 1s. a byte cannot be reprogrammed without first erasing the whole sector or block. figure 15. page program sequence sio
PM25LD512/010/ 020 confidential information chingis technology corp. 21 draft date: august, 2010, rev:0.4 device operation (continued) erase operation the memory array of the PM25LD512/010 is organized into uniform 4 kbyte sectors or 32 kbyte uniform blocks (a block consists of eight adjacent sectors) . pm25ld020 is organized into uniform 4 kbyte sectors or 64 kbyte uniform blocks (a block consists of six teen adjacent sectors) before a byte can be reprogrammed, the sector or block that contains the byte must be erased (erasin g sets bits to 1). in order to erase the devices, t here are three erase instructions available: sector erase (sector_er), block erase (block_er) and chip erase (chip_er). a sector erase operation allows an y individual sector to be erased without affecting th e data in other sectors. a block erase operation erases an y individual block. a chip erase operation erases the whole memory array of a device. a sector erase, blo ck erase or chip erase operation can be executed prior to any programming operation. sector_er command (sector erase) operation a sector_er instruction erases a 4 kbyte sector before the execution of a sector_er instruction, th e write enable latch (wel) must be set via a write enable (wren) instruction. the wel bit is reset automatically after the completion of sector an era se operation. a sector_er instruction is entered, after ce# is pulled low to select the device and stays low durin g the entire instruction sequence the sector_er instruction code, and three address bytes are input via si. erase operation will start immediately after ce # is pulled high. the internal control logic automatical ly handles the erase voltage and timing. refer to figu re 14 for sector erase sequence. during an erase operation, all instruction will be ignored except the read status register (rdsr) instruction. the progress or completion of the eras e operation can be determined by reading the wip bit in the status register using a rdsr instruction. if th e wip bit is 1, the erase operation is still in pro gress. if the wip bit is 0, the erase operation has been completed. block_er command (block erase) operation a block erase (block_er) instruction erases a 64 kbyte block of the PM25LD512/010/020. before the execution of a block_er instruction, the write enable latch (wel) must be set via a write enable (wren) instruction. the wel is reset automatically after the completion of a block erase operation. the block_er instruction code and three address bytes are input via si. erase operation will start immediately after the ce# is pulled high, otherwise the block_er instruction will not be executed. the internal control logic automatically handles the er ase voltage and timing. refer to figure 15 for block er ase sequence. chip_er command (chip erase) operation a chip erase (chip_er) instruction erases the entir e memory array of a PM25LD512/010/020. before the execution of chip_er instruction, the write enable latch (wel) must be set via a write enable (wren) instruction. the wel is reset automatically after completion of a chip erase operation. the chip_er instruction code is input via the si. erase operation will start immediately after ce# is pulled high, otherwise the chip_er instruction will not be executed. the internal control logic automatical ly handles the erase voltage and timing. refer to figu re 16 for chip erase sequence.
PM25LD512/010/ 020 confidential information chingis technology corp. 22 draft date: august, 2010, rev:0.4 device operation (continued) figure 16. sector erase sequence figure 17. block erase sequence figure 18. chip erase sequence sio sio sio
PM25LD512/010/ 020 confidential information chingis technology corp. 23 draft date: august, 2010, rev:0.4 absolute maximum ratings (1) temperature under bias -65 o c to +125 o c storage temperature -65 o c to +125 o c standard package 240 o c 3 seconds surface mount lead soldering temperature lead-free package 260 o c 3 seconds input voltage with respect to ground on all pins (2 ) -0.5 v to vcc + 0.5 v all output voltage with respect to ground -0.5 v t o vcc + 0.5 v vcc (2) -0.5 v to +6.0 v notes: 1. applied conditions greater than those listed in absolute maximum ratings may cause permanent dama ge to the device. this is a stress rating only. the funct ional operation of the device conditions that excee d those indicated in the operational sections of this speci fication is not implied. exposure to absolute maxim um rating condition for extended periods may affect device re liability. 2. maximum dc voltage on input or i/o pins is v cc + 0.5 v. during voltage transitions, input or i/o p ins may overshoot v cc by + 2.0 v for a period of time not to exceed 20 ns. m inimum dc voltage on input or i/o pins is -0.5 v. during voltage transitions, input or i/o p ins may undershoot gnd by -2.0 v for a period of ti me not to exceed 20 ns. dc and ac operating range part number PM25LD512/010/020 operating temperature (commercial grade) -40 o c to105 o c vcc power supply 2.3 v C 3.6 v dc characteristics applicable over recommended operating range from: t ac = -40c to +105c, v cc = 2.3 v to 3.6 v (unless otherwise noted). symbol parameter condition min typ max units i cc1 vcc active read current v cc = 3.6v at 33 mhz, so = open 10 15 ma i cc2 vcc program/erase current v cc = 3.6v at 33 mhz, so = open 15 30 ma i sb1 vcc standby current cmos v cc = 3.6v, ce# = v cc 10 a i sb2 vcc standby current ttl v cc = 3.6v, ce# = v ih to v cc 3 ma i li input leakage current v in = 0v to v cc 1 a i lo output leakage current v in = 0v to v cc , t ac = 0 o c to 85 o c 1 a v il input low voltage -0.5 0.8 v v ih input high voltage 0.7v cc v cc + 0.3 v v ol output low voltage i ol = 2.1 ma 0.45 v v oh output high voltage 2.3v < v cc < 3.6v i oh = -100 a v cc - 0.2 v
PM25LD512/010/ 020 confidential information chingis technology corp. 24 draft date: august, 2010, rev:0.4 ac characteristics applicable over recommended operating range from t a = -40c to +105c, v cc = 2.3 v to 3.6 v c l = 1 ttl gate and 10 pf (unless otherwise noted). symbol parameter min typ max units f ct clock frequency for fast read mode 0 100 mhz f c clock frequency for read mode 0 33 mhz t ri input rise time 8 ns t fi input fall time 8 ns t ckh sck high time 4 ns t ckl sck low time 4 ns t ceh ce# high time 25 ns t cs ce# setup time 10 ns t ch ce# hold time 5 ns t ds data in setup time 2 ns t dh data in hold time 2 ns t hs hold setup time 15 ns t hd hold time 15 ns t v output valid 8 ns t oh output hold time normal mode 0 ns t lz hold to output low z 200 ns t hz hold to output high z 200 ns t dis output disable time 100 ns t ec secter/block/chip erase time 10 ms t pp page program time 2 5 ms t vcs v cc set-up time 50 s t w write status register time (flash bit) 10 ms
PM25LD512/010/ 020 confidential information chingis technology corp. 25 draft date: august, 2010, rev:0.4 ac characteristics (continued) serial input/output timing (1) note: 1. for spi mode 0 (0,0) sio
PM25LD512/010/ 020 confidential information chingis technology corp. 26 draft date: august, 2010, rev:0.4 ac characteristics (continued) hold timing pin capacitance (f = 1 mhz, t = 25c ) typ max units conditions c in 4 6 pf v in = 0 v c out 8 12 pf v out = 0 v note: these parameters are characterized but not 10 0% tested. output test load input test waveforms and measurement level
PM25LD512/010/ 020 confidential information chingis technology corp. 27 draft date: august, 2010, rev:0.4 power-up and power-down at power-up and power-down, the device must not be selected (ce# must follow the voltage applied on vc c) until vcc reaches the correct value: - vcc(min) at power-up, and then for a further dela y of tvce - vss at power-down usually a simple pull-up resistor on ce# can be use d to insure safe and proper power-up and power-down. to avoid data corruption and inadvertent write operations during power up, a power on reset (por) circuit is included. the logic inside the device is held reset while vcc is less than the por threshold valu e (vwi) during power up, the device does not respond to any instruction until a time delay of tpuw has elap sed after the moment that vcc rised above the vwi threshold. however, the correct operation of the de vice is not guaranteed if, by this time, vcc is still be low vcc(min). no write status register, program or eras e instructions should be sent until the later of: - tpuw after vcc passed the vwi threshold - tvce after vcc passed the vcc(min) level at power-up, the device is in the following state: - the device is in the standby mode - the write enable latch (wel) bit is reset at power-down, when vcc drops from the operating voltage, to below the vwi, all write operations are disabled and the device does not respond to any write instruction. chip selection not allowed all write commands are rejected tvce read access allowed device fully accessible tpuw vcc vcc(max) vcc(min) reset state v (write inhibit) time symbol parameter min. max. unit t vce *1 vcc(min) to ce# low 10 us t puw *1 power-up time delay to write instruction 1 10 ms v wi *1 write inhibit voltage 2.1 v note : *1. these parameters are characterized only. 1.8 1. 6
PM25LD512/010/ 020 confidential information chingis technology corp. 28 draft date: august, 2010, rev:0.4 program/erase performance parameter unit typ max remarks sector erase time ms 10 from writing erase command to erase completion block erase time ms 10 from writing erase command to erase completion chip erase time ms 10 from writing erase command to erase completion page programming time ms 2 5 from writing program command to program comple tion note: these parameters are characterized and are no t 100% tested. reliability characteristics parameter min typ unit test method endurance 200,000 cycles jedec standard a117 data retention 20 years jedec standard a103 esd C human body model 2,000 volts jedec standard a114 esd C machine model 200 volts jedec standard a115 latch-up 100 + i cc1 ma jedec standard 78 note: these parameters are characterized and are no t 100% tested.
PM25LD512/010/ 020 confidential information chingis technology corp. 29 draft date: august, 2010, rev:0.4 package type information ` 8s 8-pin jedec 150mil broad small outline integrated c ircuit (soic) package (measure in millimeters)
PM25LD512/010/ 020 confidential information chingis technology corp. 30 draft date: august, 2010, rev:0.4 package type information (continued) 8k 8-contact ulta-thin small outline no-lead (wson) pa ckage (measure in millimeters)
PM25LD512/010/ 020 confidential information chingis technology corp. 31 draft date: august, 2010, rev:0.4 package type information (continued) package type information (continued)
PM25LD512/010/ 020 confidential information chingis technology corp. 32 draft date: august, 2010, rev:0.4
PM25LD512/010/ 020 confidential information chingis technology corp. 33 draft date: august, 2010, rev:0.4 revision history date revision no. description of changes page no . march, 2009 0.0 preliminary product specification all september, 2009 0.1 1. modify the program frequency to 50mhz 2. improve erase time from 15ms to 10ms. 1,10 october, 2009 0.2 1. modify the t hs , t hd to 15ns 24 october, 2009 0.3 1. fix the erase time november, 2009 0.31 1. change the operation voltage spec 2.3v~2.8v all august, 2010 0.4 1. modify the operation voltage 2. 3v~3.6v 2. modify the write inhibit 1.6v~1.8v all

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